PCI was originally designed to be used in a wide range of systems from notebooks to high-end servers. There are now a wide range of new buses being developed to replace PCI, which enable cost-savings, performance enhancement, and specialized features. HyperTransport is a new bus that deals specifically with chipset interconnect, the high-speed link between the memory and IO controller chips. HyperTransport Architecture allows hardware and low-level software designers, engineers, and technicians to get up to speed quickly on this new bus protocol, without having to wade through specifications and white papers. The book organizes topics in a logical, tutorial format which quickly guides the reader through the major features of the specification. Numerous diagrams and examples reduce the more complicated concepts to manageable proportions and allow the reader to see the important relationships along the way.
From the Back Cover
HyperTransport™ (HT) technology promises to revolutionize connectivity for computers, servers, embedded systems, and networking and tele-communications equipment. It is a high-speed, low latency, point-to-point, packetized link that enables chips to transfer data at peak rates of up to 12.8 Gigabytes per second, far greater than existing bus technologies. Furthermore, HyperTransport improves reliability and reduces board design complexity. It is scalable and compatible with legacy PC buses, SNA, and PCI.
HyperTransport™ System Architecture provides a comprehensive, technical guide to HyperTransport technology. It opens with an overview of HT systems, highlighting the technology’s fundamental principles, basic architecture, and its many advantages. The book goes on to detail all facets of HyperTransport systems, including the protocol, I/O, routing, configuration, and more. It also features important performance considerations and addresses critical compatibility issues.
Essential topics covered include:
- Signal groups
- Packet protocol, covering control and data packets
- HT flow control, and how it differs from PCI flow control
- I/O ordering rules, including upstream, downstream, and host ordering requirements
- Interrupts, error detection, and error handling
- HT system management
- Routing packets, covering point-to-point topology and HT’s fairness algorithm
- Device configuration
- The electrical environment, including power requirements and signaling characteristics
- HyperTransport bridges
- Double-hosted chains
- Anticipated networking extensions
- PCI, PCI-X, AGP, and X86 compatibility issues
A chapter is dedicated to transaction examples illustrating the practical application of HyperTransport technology.
A MindShare PC System Architecture Series book, HyperTransport™ System Architecture provides complete, authoritative, and detailed information necessary for developers, networking professionals, and anyone interested in implementing and deploying HT systems.
MindShare’s PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel. Each title explains the architecture, features, and operations of systems built using one particular type of chip or hardware specification.
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